(1) Field of the Invention
The invention relates to a magnetic RAM device and, more particularly, to a magnetic RAM device based on a magnetic tunnel junction cell.
(2) Description of the Prior Art
Magnetic memory devices, based on magnetic tunnel junction (MTJ) cells, are an important new type of memory technology. Magnetic RAM arrays can be formed on an integrated circuit to provide non-volatility, high speed, low writing energy, infinite write cycles, and immunity to radiation. These advantages make magnetic RAM a technology with great promise.
Referring now to FIG. 1, models of magnetic tunnel junction cells 10 and 30 are illustrated. A magnetic tunnel junction cell 10 and 30 comprises a pinned layer 14, a free layer 18, and a dielectric layer 22. Typically, the free layer 18 and the pinned layer 14 comprise ferromagnetic materials that can be magnetically oriented. The free layer 18 is configured such that the magnetic orientation can be changed, or rotated, by exposure to an external magnetic field. The pinned layer 14 is configured such that the magnetic orientation is fixed and will not respond to a typical magnetic field. The dielectric layer 22 typically comprises a relatively thin oxide layer capable of electrically isolating the free layer 18 from the pinned layer 14 at low potentials and capable of conducting current through electron tunneling at higher potentials. The dielectric layer 22 may be called a tunnel layer.
In the first MTJ cell 10, the pinned layer 14 and the free layer 18 are magnetically oriented in opposite directions. In the second MTJ cell 30, the pinned layer 14 and the free layer 18 are magnetically oriented in the same direction. If the same current value ICONSTANT 32 is forced through each cell 10 and 30, it is found that the first cell 10 voltage V1 is larger than the second cell 30 voltage V2. In general, the resistance of an opposite-oriented MTJ cell 10 is greater than the resistance of a same-oriented MTJ cell 30. Binary logic data (‘0’ and ‘1’) can be stored in a MTJ cell and retrieved based on the cell orientation and resulting resistance. Further, since the stored data does not require a storage energy source, the cell is non-volatile.
Referring now to FIG. 2, the program scheme of a prior art, MTJ cell 10 is illustrated. The MTJ cell 10 is electrically coupled to a bit line (BL) 40 overlying the free layer 18. A program line (PL) 48 runs under the MTJ cell 10. However, the PL 48 is electrically isolated from the MTJ cell 10 by a dielectric material such that a large gap 58 exists. To program the cell, PL 48 conducts a writing current IWRITE to generate magnetic field HDATA 52. The direction of HDATA 52 depends on the direction of IWRITE. In addition, an assist current IASSIST is conducted by the BL 40. IASSIST generates a magnetic field HASSIST 56 that is orthogonal to the longitudinal axis of the cell 10. The HASSIST 56 field assists the HDATA 52 field in switching the magnetic orientation of the free layer 18 but will not program the cell without the HDATA 52 field generated by the program line 48. Therefore, the cell 10 at the intersection of an active program line 48 and an active bit line 40 is programmed.
There are two significant problems with this design. First, the magnetic coupling between the PL 48 and the cell 10 is not optimal due to the gap 58. Therefore, a large writing current IWRITE must be used to generated adequate field strength. This large writing current can approach the electromigration limit of the conductor and prevents downward scaling of the RAM cell 10. Second, there can be many other non-selected cells that are exposed to magnetic fields generated by the active program line 48 and bit line 52.
Referring now to FIG. 3, an exemplary MRAM array 60 is illustrated. A 2×2 array of cells is shown. Each cell comprises a MTJ cell and a transistor as shown by R066 and M064, R170 and M168, R274 and M272, R378 and M376. Each transistor is coupled to a word line signal Wn 82 or Wn+1 86. A cell is written by asserting the word line of that cell, forcing a reading current through the bit line of that cell, and then measuring the voltage on that bit line. For example, to read the state of MTJ cell R170, the word line Wn 82 is asserted to turn ON M168. The free layer of R170 is thereby coupled to ground 80 through M168. Next, the reading current is forced on bit line Bn+1 94. Since only reading transistor M168 is turned ON, the reading current flows through the R1 cell 70 to ground 80. The voltage of Bn+1 is then measured to determine the state (‘0’ or ‘1’) of the cell R170. Each cell has one reading transistor. Therefore, this type of MRAM architecture is called ‘1T1R’.
The cells are written using the method described above and illustrated in FIG. 2. Referring again to FIG. 3 and for example, the MTJ cell R274 is written by forcing the writing current through the programming line PLn+1 86 and the assist current though the bit line Bn 90. PLn+1 86 and Bn 90 intersect at cell R274 such that R2 is programmed. However, note that PLn+1 98 also runs under the non-selected cell R378. Therefore, cell R3 is “half-selected.” The magnetic field generated by PLn+1 98 can disturb, or flip, the state of R378. In addition, Bn 90 also couples to the non-selected cell R066. The assist field created by Bn 90 can disturb the state of R066. These “half-select” disturbances can cause loss of data or change of switching thresholds.
Referring now to FIG. 4, a second prior art MRAM array architecture 100 is illustrated. This array 100 uses two transistors for each MTJ cell and is called a 2T1R array. To improve the programming efficiency, the programming current runs through the MTJ cell directly through the pinned layer or through a conductive layer laminated to the pinned layer. By running the programming current in the MTJ instead of in an adjacent conductor, the magnetic coupling is improved such that the programming current can be reduced to about ⅕ the level of the cell illustrated in FIG. 2. Referring again to FIG. 4, the programming current path is changed such that the longitudinal axis of the cell is orthogonal to the writing current path. In this way, the cells can be programmed solely by the magnetic field generated by the programming current without an assist field.
For example, the program cell R1108, word line W1 is asserted to turn ON transistors M3109 and M4110. Next, a writing current is passed through cell R1108 either from P2134 to P2′ 138 or from P2′ 138 to P2134. The writing current will generated a magnetic field to orient the free layer in R1108. Note that there are no half-selected cells since the programming current only flows through the selected cell. Each MRAM cell in this array 100 requires two transistors, two programming lines, a bit line, and a word line. While this MRAM architecture is a significant improvement over the previous art shown in FIGS. 1-3, the addition of a transistor to each cell is a significant disadvantage. Further, since both transistors must carry a large programming current, the transistors must be relatively large. In fact, the writing transistors occupy most of the cell area.
Several prior art inventions relate to magnetic RAM devices. U.S. Pat. No. 6,418,046 B1 to Naji teaches an architecture for a MRAM. The MRAM cell is programmed by flowing currents through metal bit lines and digit lines intersecting at the magnetic tunnel junction (MTJ) device. U.S. Pat. No. 6,335,890 B1 to Reohr et al discloses a MRAM architecture where write lines are segmented to reduce cell interference during programming. U.S. Pat. No. 6,272,041 B1 to Naji describes a MTJ MRAM series-parallel architecture. U.S. Pat. No. 6,421,270 B1 to Tai discloses a magneto-resistive RAM.